SPECULATIVE REFERENCE DESIGN — NOT AN INTEL OR CORINTIS PRODUCT
Pablo’s Chip
XBM-14A / CX-1
A 3.2 kW accelerator package built on Intel 14A compute tiles, EMIB-T bridges, and 12 stacks of Intel’s patented cross-batch memory — cooled by a three-tier Corintis microfluidic system that treats the memory base die, not the logic, as the hardest thermal problem.
- Package
- 120 × 180 mm, glass substrate
- Compute
- 4 × 14A tile, High-NA EUV
- Memory
- 12 × XBM 16-high, 576 GB
- Cooling
- Corintis 3-tier co-packaged
- Earliest plausible
- 2030+
Cross-section
Tier 1 · zoned microfluidic lid16 independently solved flow zones · 80 µm pitch Cu, Glacierware-generated
The lid is not a cold plate with one flow path. Sixteen zones are solved independently so the coolant arrives cold where the flux is highest, instead of arriving pre-heated after crossing the compute tiles. Loop A reaches the DRAM stacks cold-first — the 85 °C refresh ceiling is tighter than the logic ceiling, so it gets first claim on the coldest water.
Tier 2 · backside channels in 14A siliconCoolant ~50 µm from junction
Channels etched into the back of the compute die put coolant roughly 50 µm from the junction. This is what makes the 400 W/cm² matrix-engine hotspots survivable: at that distance the silicon between heat source and fluid stops being the dominant thermal resistance.
14A tile 0600 W · 400 W/cm² pk
One of four Intel 14A compute tiles on High-NA EUV. 600 W each, 2,400 W across the four. Average flux is a manageable 120 W/cm²; the problem is the peak — matrix-engine hotspots hit 400 W/cm², which is where Tier 2 zone-solving stops being a nicety.
14A tile 1600 W · 400 W/cm² pk
Identical to tile 0. Tiles are bridged with EMIB-T at 25 µm bump pitch rather than sitting on a full-surface silicon interposer — cheaper and shorter, but it removes a lateral heat-spreading path the package would otherwise have had for free.
× 16 tiers XBM · BEOL 1T1C DRAM≤ 85 °C · 12 stacks, 576 GB total
Cross-batch memory built as 1T1C DRAM in the back end of line — thin-film transistors in the metal stack rather than front-end silicon. Twelve stacks, sixteen high, 420 W in aggregate at a mild 18 W/cm². The tier is thermally easy and structurally hard: retention, leakage and repair behaviour all differ from conventional DRAM at this height.
UCIe base die32 GT/s SerDes · ~90 W in 40 mm² · 1,080 W across 12
The whole reason this package is interesting. Serialising the memory interface concentrates I/O power into the base die instead of spreading it across PHY on the SoC edge: ~90 W in 40 mm² is 225 W/cm², buried under sixteen DRAM tiers. Top-side cooling cannot reach it, which is what forces Tier 3 to exist.
Tier 3 · riserLateral extraction from the base die
The load-bearing invention, and the only part of this design with no public demonstration behind it. Pulling heat sideways out of a base die buried under sixteen tiers is a research problem, not a product. Everything above it in this stack is incremental engineering; if the riser does not work, the package does not exist.
Glass substrate · EMIB-T25 µm bump pitch · 120 × 180 mm, 12+ reticle-class silicon area
A 120 × 180 mm glass substrate carrying more than twelve reticles of silicon. Glass buys dimensional stability at this size; dropping the interposer for bridges buys z-height, which is what leaves a stack alley wide enough for the riser to fit at all.
OAM-class carrierQuick-disconnect coolant fittings at card edge
Coolant enters at 45 °C facility water — no chiller — and leaves at 60 °C, warm enough to be worth recovering. About 6 L/min for the whole ~4.2 kW package. The fittings are also the commercial problem: liquid inside a $40k package is a warranty question long before it is a physics question.
Each layer carries a design decision, not just a label. Click or tab to any block in the drawing to open it. Layer thicknesses are schematic, not to scale. Colour encodes steady-state temperature class, per the legend above.
Thermal budget
Modeled — illustrative, not simulated
| Zone | Power | Flux | Ceiling | Cooling tier | Margin |
|---|---|---|---|---|---|
| 4 × 14A compute tile | 2,400 W | 120 W/cm² avg | 105 °C Tj | Tier 1 + 2 | wide |
| Matrix-engine hotspots | — | 400 W/cm² pk | 105 °C Tj | Tier 2, zone-solved | tight |
| 12 × XBM DRAM tiers | 420 W | 18 W/cm² | 85 °C | Tier 1, Loop A cold-first | wide |
| 12 × UCIe base die | 1,080 W | 225 W/cm² | 95 °C | Tier 3 riser only | critical |
| Substrate, VR, leakage | ~300 W | low | — | Tier 1 spillover | wide |
| Package total | ~4.2 kW | — | — | 45 °C in / 60 °C out | ~6 L/min |
The inversion
Why XBM changes the cooling problem
| HBM4 package | XBM package | Consequence | |
|---|---|---|---|
| Interface | ~2,048-bit parallel, slow | Serial UCIe, 32 GT/s | Interface power concentrates instead of spreading |
| Where I/O power sits | Split across PHY on the SoC edge | In the memory base die | New hotspot appears under the memory |
| Interposer | Silicon, full-surface | None — bridges only | Loses a large lateral heat-spreading path |
| Z-height | Taller, stiffeners | Shorter, no stiffeners | Room for a riser in the stack alley |
| Thermal binding constraint | DRAM refresh at 85 °C | Base-die SerDes at 95 °C | Top-side cooling stops being sufficient |
What kills it
Ranked by how fast it is fatal
Fatal if unsolved
The riser is fiction
Tier 3 is the only part of this design with no public demonstration behind it. Lateral extraction from a base die buried under sixteen tiers is a research problem, not a product. Everything above it is incremental; this is the load-bearing invention.
Fatal if unsolved
Coolant inside a $40k package
Warranty, not physics. A hyperscaler designing its own silicon absorbs leak risk on its own fleet. A merchant foundry selling this to third parties absorbs it on someone else’s, and gets an RMA queue for the privilege.
Schedule risk
Two timelines that barely touch
14A hits volume in 2028. XBM is a December 2024 patent filing with commercialization talked about at 2030 or later. A package needing both is a 2030-at-the-earliest object, and only if Intel actually re-enters DRAM.
Schedule risk
BEOL DRAM is unproven at 16-high
Thin-film transistors in the metal stack change retention, leakage, and repair behaviour versus front-end silicon. Intel’s own answer is built-in self-repair and spare channels — which is a yield admission, and yield admissions carry thermal margin costs.
Structural
The board seat cuts both ways
Lip-Bu Tan sits on Corintis’ board personally. That aligns the thinking and complicates the paperwork: any Intel–Corintis commercial agreement runs through recusal and arm’s-length review before it runs through engineering.
Structural
Intel may just build it
Intel has its own packaging thermal program and has already shown segmented heat spreaders for kilowatt-class parts. The buy case rests on Corintis’ flow-optimization software and copper microfabrication, not on the physics, which Intel understands perfectly well.
Speculative engineering exercise. Intel has announced no XBM product, no Corintis relationship, and no co-packaged cooling offering; XBM exists as a patent application published 2 July 2026. Public anchors used: Intel EMIB-T scaling and 120 × 180 mm package roadmap; Intel 14A PDK 0.9 targeted October 2026 with volume in 2028; the XBM patent’s 1T1C BEOL DRAM, 0.5–5 GB dies, 8–16-high stacks, and 32 GT/s UCIe base-die I/O; and the Microsoft–Corintis in-chip microfluidic result. Every power, flux, flow, and temperature figure above is the author’s estimate.